The present invention relates in general to integrated circuits and, more particularly, to a non-overlapping clock generator having synchronized clock transitions.
Signal processing functions are often implemented more economically using digital rather than analog methods. For example, a wireless communication device such as a cellular telephone or pager often uses fewer external tuning components if a transmitted carrier signal is converted to digital data at an early stage in the receiver of the communication device. A high frequency analog-to-digital converter (ADC) is used to convert the analog carrier signal to digital data. A preprogrammed mathematical demodulation algorithm extracts a demodulated signal from the digital data.
A typical high frequency ADC includes a plurality of parallel, time-interleaved, ADC channels which sample the analog carrier signal at alternating sampling points defined by the trailing edges of alternate clock phases. The alternate clock phases are non-overlapping to prevent a race condition from occurring. Each channel produces a data word representative of the amplitude of the carrier signal at the sampling point. A digital output data stream is formed by interleaving data words from each channel.
A low error rate in the digital data requires symmetry among the parallel channels, including carefully matched components and timing signals. More specifically, an accurate representation of the carrier signal by the data stream depends on the carrier signal being sampled at equal time intervals. Accordingly, the alternate non-overlapping clock phases typically are referenced to a system clock. However, the clock phases are coupled through asymmetrical signal paths in the clock generator. The asymmetrical signal paths have different propagation delays due to having a different number of logic gates. The different propagation delays result in a relative phase shift in the trailing edges of the clock phases and in the carrier signal being sampled at unequal intervals. Therefore, spurious errors are generated in the digital data stream.
Hence, there is a need for a clock circuit which generates multiple non-overlapping clock phases whose trailing edges are synchronized to occur at equally spaced time intervals.